1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming V0 structures for semiconductor devices by forming a protection layer with a non-uniform thickness and various semiconductor devices having the resulting V0 structural configurations.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Generally, in complex circuitry including complex logic portions, MOS technology is presently a preferred manufacturing technique in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits fabricated using MOS technology, field effect transistors (FETs), such as planar field effect transistors and/or FinFET transistors, are provided that are typically operated in a switched mode, i.e., these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years, particularly the channel length of transistor devices. As a result of the reduced dimensions of the transistor devices, the operating speed of the circuit components has been increased with every new device generation, and the “packing density,” i.e., the number of transistor devices per unit area, in such products has also increased during that time. Such improvements in the performance of transistor devices has reached the point where one limiting factor relating to the operating speed of the final integrated circuit product is no longer the individual transistor element but the electrical performance of the complex wiring system that is formed above the device level where the actual semiconductor-based circuit elements, such as transistors, are formed in and above the semiconductor substrate.
Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections or “wiring arrangement” for the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured. Accordingly, the various electrical connections that constitute the overall wiring pattern for the integrated circuit product are formed in one or more additional stacked so-called “metallization layers” that are formed above the device level of the product. These metallization layers are typically comprised of layers of insulating material with conductive metal lines or conductive vias formed in the layers of material. Generally, the conductive lines provide the intra-level electrical connections, while the conductive vias provide the inter-level connections or vertical connections between different levels. These conductive lines and conductive vias may be comprised of a variety of different materials, e.g., copper, with appropriate barrier layers, etc. The first metallization layer in an integrated circuit product is typically referred to as the “M1” layer, while the conductive vias that are used to establish electrical connection between the M1 layer and lower level conductive structures (explained more fully below) are typically referred to as “V0” vias. The conductive lines and conductive vias in these metallization layers are typically comprised of copper, and they are formed in layers of insulating material using known damascene or dual-damascene techniques. Additional metallization layers are formed above the M1 layer, e.g., M2/V1, M3/V2, etc. Within the industry, conductive structures below the V0 level are generally considered to be “device-level” contacts or simply “contacts,” as they contact the “device” (e.g., a transistor) that is formed in the silicon substrate.
FIG. 1A is a cross-sectional view of an illustrative integrated circuit product 10 comprised of a plurality of transistor devices 15 formed in and above a semiconductor substrate 12. A schematically depicted isolation region 13 has also been formed in the substrate 12. In the depicted example, the transistor devices 15 are comprised of an illustrative gate structure, i.e., a gate insulation layer 16 and a gate electrode 18, a gate cap layer 20, a sidewall spacer 22 and simplistically depicted source/drain regions 24. At the point of fabrication depicted in FIG. 1A, layers of insulating material 17A, 17B, i.e., interlayer dielectric materials, have been formed above the product 10. Other layers of material, such as contact etch stop layers and the like, are not depicted in the attached drawings. Also depicted are illustrative source/drain contact structures 28 which include a combination of a so-called “trench silicide” (TS) region 28A and a metal region 28B (such as tungsten). In the depicted process flow, the upper surface of the source/drain contact structures 28 is approximately planar with the upper surface of the gate cap layers 20. Also depicted in FIG. 1A are a plurality of so-called “CA contact” structures 32 and an illustrative gate contact structure 31 which is sometimes referred to as a “CB contact” structure. The CA contact structures 32 and the CB contact structure 31 are formed to provide electrical connection between the underlying devices and the V0 via level. The CA contact structures 32 are formed to provide electrical contact to the source/drain contact structures 28, while the CB contact 31 is formed so as to contact a portion of the gate electrode 18 of one of the transistors 15. In a plan view (not shown), the CB contact 31 is positioned vertically above the isolation region 13, i.e., the CB contact 31 is not positioned above the active region defined in the substrate 12. The CA contact structures 32 may be in the form of discrete contact elements, i.e., one or more individual contact plugs having a generally square-like or cylindrical shape, that are formed in an interlayer dielectric material, as shown in FIG. 1A. In other applications (not shown in FIG. 1A), the CA contact structures 32 may also be a line-type feature that contacts underlying line-type features, e.g., the source/drain contact structures 28 that contact the source/drain region 24 and typically extend across the entire active region on the source/drain region 24. Typically, the CB contact 31 is in the form of a round or square plug.
In one embodiment, the process flow of forming the source/drain contact structures 28, CA contacts 32 and CB contact 31 may be as follows. After a first layer of insulating material 17A is deposited, source/drain contact openings are formed in the first layer of insulating material 17A that expose portions of underlying source/drain regions 24. Thereafter, traditional silicide 28A is formed through the source/drain contact openings, followed by forming a metal 28B (such as tungsten) on the metal silicide regions 28A, and performing a chemical mechanical polishing (CMP) process down to the top of the gate cap layer 20. Then, a second layer of insulating material 17B is deposited. In older devices, the packing density was such that the openings in the layer of insulating material 17B for both the CA contact structures 32 and the CB contact structure 31 could be formed using a single patterned etch mask. However, as packing densities have increased with newer device generations, the openings in the layer of insulating material 17B for the CA contact structures 32 and the CB contact structure 31 are formed separately using two different masking layers—a CA masking layer and a CB masking layer. Thus, in one illustrative process flow, using the CA masking layer, the contact openings for the CA contacts 32 are formed first in the second layer of insulating material 17B so as to expose portions of the tungsten metallization 28B of the underlying source/drain contact structure 28. Then the CA masking layer is removed and the CB masking layer is formed over the second layer of insulating material 17B and in the previously formed CA contact openings formed therein. Next, using the CB masking layer, the opening for the CB contact 31 is formed in the second layer of insulating material 17B and through the gate cap layer 20 so as to expose a portion of the gate electrode 18. Thereafter, the CB masking layer is removed and the CA contacts 32 and the CB contact 31 are formed in their corresponding openings in the second layer of insulating material 17B by performing one or more common metal deposition and CMP process operations, using the second layer of insulating material 17B as a polish-stop layer to remove excess material positioned outside of the contact openings. The CA contacts 32 and CB contact 31 typically contain a uniform body of metal, e.g., tungsten, and may also include one or more metallic barrier layers (not shown) positioned between the uniform body of metal and the layer of insulating material 17B. The source/drain contact structures 28, the CA contacts 32 and the CB contact 31 are all considered to be device-level contacts within the industry.
Also depicted in FIG. 1A is the first metallization layer—the so-called M1 layer—of the multi-level metallization system for the product 10 formed in a layer of insulating material 34, e.g., a low-k insulating material. A plurality of conductive vias—so-called V0 vias 40—are provided to establish electrical connection between the device-level contacts—CA contacts 32 and the CB contact 31—and the M1 layer. The M1 layer typically includes a plurality of metal lines 38 that are routed as needed across the product 10.
FIGS. 1B-1F depict a semiconductor device with self-aligned contacts where a line-type CA structure 30 (FIG. 1C) was formed using one illustrative prior art technique. In this illustrative example, the CA contact structure 30 is not formed in a separate layer of insulating material, as was the CA contact structures 32 (in the layer 17B) described above. Rather, in this process flow, the upper metal portion of the source/drain contact structure (positioned below the level of the gate cap layers 20) serves as the “CA contact structure.” In this process flow, only the CB contact is formed above the gate cap layers 20 in a separate layer of insulating material. That is, using this process flow, the formation of a separate CA contact in a layer of insulating material positioned above the level of the gate cap layers 20 is omitted, and only a single masking layer—the CB masking layer—is used to form the equivalent of the CA contacts 32 and the gate contact 31 described above. However, relative to the process flow described in connection with FIG. 1A above, this process flow does require the formation of an extended-length V0 via to contact the CA contact structure 30, as described more fully below.
FIG. 1B depicts an illustrative prior art integrated circuit product 10 comprised of first and second transistors 15A, 15B formed in and above a semiconductor substrate 12. In the depicted example, each of the transistors 15A, 15B is comprised of the gate insulation layer 16 and the gate electrode 18, the gate cap layer 20 and a sidewall spacer 22. Typically, the gate cap layer 20 and the sidewall spacer 22 are made of a material such as silicon nitride and their purpose is to effectively encapsulate and protect the gate structure. The gate structure may be formed using either gate first or replacement gate techniques. In the case where the gate structure is formed using replacement gate techniques, the cap layer 20 is formed after a sacrificial gate structure (not shown) is removed and after a replacement gate structure (e.g., high-k insulation layer and one or more metal layers is formed in the position previously occupied by the removed sacrificial gate structure). With continuing reference to FIG. 1B, also depicted are illustrative raised source/drain regions 24 and a layer of insulating material 26 (e.g., silicon dioxide) that is formed above the product 10 and planarized.
FIGS. 1B-1F will only depict the formation of a source/drain contact structure between the gate structures 15A, 15B so as to facilitate explanation. Those skilled in the art will appreciate that, in practice, a corresponding source/drain contact structure will be formed for all of the source/drain regions, i.e., on the source/drain region to the left of the gate structure 15A and on the source/drain region to the right of the gate structure 15B.
Accordingly, FIG. 1C depicts the product 10 after several process operations were performed to form a so-called self-aligned contact that is conductively coupled to the raised source/drain region 24. First, a patterned etch mask (not shown) was formed above the product 10 so as to expose the area between the gate structures 15A-15B. Thereafter, at least the insulating material 26 was etched selectively relative to the sidewall spacers 22 and the gate cap layer 20 to thereby expose the raised source/drain region 24. Next, the patterned etch mask was removed and a trench silicide structure 28A was formed on the exposed source/drain region 24 by performing traditional silicide processing operations. Thereafter, a line-type CA contact structure 30 comprised of, for example, tungsten, was formed so as to be conductively coupled to the trench silicide structure 28A. In one embodiment, the line-type CA contact structure 30 may be formed of a material such as tungsten and it may extend across substantially the entire active region of the substrate 12, just like the trench silicide structure 28A. In one particular example, the line-type CA contact structure 30 may be formed by overfilling the area above the trench silicide structure 28A with tungsten and thereafter performing a CMP process.
FIG. 1D depicts the product 10 after several process operations were performed. First, a layer of material 32 having a substantially uniform thickness was formed above the product depicted in FIG. 1C. The substantially uniform thickness of the layer of material 32 may vary depending upon the particular application. In one example, the layer of material 32 may be a material such as N-block (SiCNH). Thereafter, a patterned layer of insulating material 34, such as a low-k material (k value less than 3.3), having an opening 34A formed therein, was formed above the layer of material 32. The product depicted in FIG. 1D is the result of initially blanket depositing the layer of insulating material 34 above the product 10, and thereafter patterning the layer of material 34 through a patterned etch mask (not shown) so as to form the patterned layer of insulating material 34, with the opening 34A, as depicted in FIG. 1D.
FIG. 1E depicts the product 10 after several process operations were performed. First, the layer of material 32 was patterned using a patterned etch mask (not shown) so as to define the opening 32A, as depicted in FIG. 1E. The opening 32A is for the conductive V0 via 40 that will be subsequently formed therein. Ideally, the opening 32A will be relatively large in the lateral width direction so that the resulting V0 via 40 will also be relatively large—a “fat” V0. A relatively larger V0 is desirable in that it reduces the electrical resistance of the V0 structure 40 and it makes it easier to actually contact the underlying CA contact 30, i.e., the chances of missing the CA contact 30 decrease if the V0 via is relatively wide. Then, the conductive lines 38 and conductive V0 vias 40 were formed in the openings 34A, 32A, respectively, by depositing one or more conductive materials, e.g., barrier layers and copper, and performing a polarization process to remove excess conductive materials positioned outside of the opening 34A. FIG. 1E depicts an idealized V0 structure 40 that results when the etch process that is performed to form the opening 32A in the material layer 32 is timed perfectly such that there is effectively no consumption of the underlying gate cap layers 20 exposed by the opening 32A. Note that, in this process flow, the V0 via must extend down to at least the level of the upper surface of the gate cap layer 20 so that electrical contact may be made to the CA contact 30.
FIG. 1F depicts a situation wherein the idealized V0 structure 40 depicted in FIG. 1D is not achieved. As noted above, the opening 32A in the material layer 32 is formed such that it is relatively wide so that the ultimate V0 via will also be relatively wide or “fat.” As shown in FIG. 1F, the width of the opening 32A is such that it typically overlaps the gate cap layer 20 of one or both of the transistors, as indicated by the dimensioned arrows 35. Unfortunately, there is typically little etch selectivity between the material of the material layer 32, which is frequently N-block, and the material of the gate cap layers 20, which is typically silicon nitride. As a result, if the etch process that is performed to form the opening 32A in the material layer 32 is not timed perfectly, some or all of the underlying gate cap 20 may also be consumed, thereby exposing a portion of the gate electrode 18. As a result, when the V0 via 40 is formed, the V0 via 40 may actually contact the exposed gate structures 18, as indicated in the dashed lines 37. Such a situation results in an electrical short between at least the V0 structure 40 (and perhaps the CA contact 30) and the gate electrode 18. Such a situation can result in complete device failure.
The present disclosure is directed to various methods of forming V0 structures for semiconductor devices, and various semiconductor devices having the resulting V0 structural configurations, that may solve or reduce one or more of the problems identified above.